In memories and LSI(large-scale integrated circuit) such as a microprocessor, which are known as the representative of semiconductor devices, the dimensions of device have been increasingly fine-structured with an increase in integration density. Also, the semiconductor region to compose the device has been formed shallower. Further, when forming a contact in semiconductor region, the size of contact hole to be formed in interlayer dielectric film has been also limited.
For example, in recent LSI that is composed of MOS (metal oxide semiconductor), when forming a contact in semiconductor region composed of a source region and a drain region, the size of the contact hole to be formed in the interlayer dielectric film is designed to be a fine value of less than 0.4 .mu.m (in diameter). As the contact hole is fine-structured like this, the kind of materials for upper wiring layer that can be formed well-adhesive to the contact hole is limited. Tungsten (W) is known as one of the excellent wiring materials applicable to such object. Here, when forming a contact in semiconductor region, if a wiring material of tungsten is adhered directly to the semiconductor region, the contact characteristic is deteriorated due to the reaction of the semiconductor region and tungsten. To prevent this, a high-melting-point metal layer to function as the barrier layer has been laid between them. As the high-melting-point metal layer, a two-layer film of Ti/TiN with excellent barrier performance is generally used. Ti (titanium) is formed on the semiconductor region side and TiN (titanium-nitride) is formed on the tungsten side. Tungsten has a characteristic easy to adhere to TiN.
Also, in the case of forming a contacting a shallow semiconductor region, an increase in contact resistance becomes an issue. It is known that to form a silicide layer such as Co--Si alloy (CoSi.sub.2), a silicide compound, on the surface of the semiconductor region is effective in restraining the contact resistance from increasing.
Problems occurred when the contact resistance increases are explained below. FIG. 1 is an illustrative cross sectional view showing the electrode part of a MOS transistor composing LSI. In FIG. 1, 101 is a Si substrate, 102 is a source region, 104 is a channel region, 105 is a gate oxide film, 106 is a sidewall oxide film, 107 is a gate electrode, 108 is an interlayer dielectric film, 109 is a contact hole, 110 is a barrier layer compose of two-layer film of Ti/TiN, 111 is a wiring layer of tungsten, and 112 is an upper wiring layer of Al-system metal.
Here, the resistance parasitic to the current path when the MOS transistor is turned on is classified into components listed below.
Rc: resistance inside the contact hole (in this case, a resistivity of tungsten, which is reversely proportional to the square of the diameter of contact hole) PA1 Rx: contact resistance of the barrier layer and the silicide layer (reversely proportional to the square of the diameter of contact hole) PA1 Rs: resistance of the silicide layer PA1 Rms: contact resistance of the silicide layer and the source/drain region PA1 Rch: channel resistance PA1 a substrate; PA1 a semiconductor region formed on the substrate; and PA1 a silicide layer as a contact layer formed directly contacting the semiconductor region; PA1 wherein the silicide layer is made to be rich in silicon while including such a silicon amount that contact resistance is significantly lowered. PA1 forming selectively a given conductive type semiconductor region on a substrate; PA1 forming a Co--Si alloy layer on the entire surface of the semiconductor region; PA1 introducing Si into the entire surface or part of the Co--Si alloy layer; PA1 forming a Ti-included layer in part of the Co--Si alloy layer; and PA1 conducting the thermal treatment of the substrate to react the introduced Si with the Co--Si alloy layer and the Ti-included layer to form a Si-rich silicide layer including such a silicon amount that contact resistance is significantly lowered.
The total resistance Rt when the MOS transistor is turned on is given by expression 1: EQU Rt=2Rc+2Rx+2Rs+2Rms+Rch [1]
The contact resistance Rco is given by expression 2: EQU Rco=Rc+Rx [2]
In FIG. 1, as the dimensions of the MOS transistor decrease with an increase in integration density of LSI, especially Rx abruptly increases in reverse proportion to the square of the diameter of contact hole, and therefore the contact resistance Rco increases based on expression 2. Along with this, the total resistance Rt increases based on expression 1 and thereby on-current decreases. Therefore, a problem occurs in that the operation speed of the entire LSI is lowered. This is because the amount of electric charge supplied to the next-stage element (transistor) decreases due to the decrease in on-current.
Semiconductor devices where a silicide layer composed of Co--Si alloy layer is formed in its semiconductor region so as to restrain the contact resistance from increasing are, for example, disclosed in Japanese patent application laid-open No. 7-78788 (1995), and H. Kawaguchi et al., "A Robust 0.15 .mu.m CMOS Technology with CoSi.sub.2 Salicide and Shallow Trench Isolation", 1997 Symposium on VLSI Technology Digest of Technical Papers 9B-4 (1997) pp. 125-126.
FIG. 2 shows an example of semiconductor device described in Japanese patent application laid-open No. 7-78788. Between a lower conductor region 202 as source/drain region formed in a semiconductor substrate 200 and an upper wiring layer 206 formed on insulating layers 204A, 204B on a gate electrode 220 to cover the lower conductor region 202, there is provided electrical connection through a connection hole (intermediate conductor layer) 208. The connection hole 208 is composed of a monocrystal CoSi.sub.2 (Co--Si alloy) layer 210 formed on the surface of the lower conductor region 202, a tungsten layer 214 as a wiring material deposited (buried) in a contact hole 212 formed in the insulating layers 204A, 204B, and a monocrystal TiN layer 216 formed between the layers 210 and 214. Here, the monocrystal TiN layer 216 functions as a barrier layer to control the reaction of the lower conductor region 202 and the tungsten layer 214. Under the upper wiring layer 206, there is formed a barrier layer 218 of two-layer film of Ti, TiON from below.
However, in the conventional technique described in Japanese patent application laid-open No. 7-78788, there is a problem that the silicide layer of Co--Si alloy layer used as the contact layer does not sufficiently play a role to suppress an increase in contact resistance (Rx). This is because the Si content of the Co--Si alloy layer or a Co--Si--Ti alloy layer to be formed through the reaction of the Co--Si alloy layer and Ti as the component of the barrier layer formed on the Co--Si alloy layer is small.